The present disclosure relates generally to electronic device displays, and, more particularly, to reducing non-uniformity in the gate insulator of an oxide thin-film-transistor (TFT).
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
During the fabrication of electronic device displays, numerous masks may be used to define areas of deposition and/or etching to create patterned materials on the TFT backplanes. For example, materials may be dry-etched using a plasma etching machine on an area that is masked. Further wet-etching may pattern masked areas by use of certain chemicals, such as oxalic acid. Unfortunately, during the etching process, certain portions of the TFT may be inadvertently etched away. For example, the surface of a gate insulation layer may be etched away. The gate insulation layer may insulate the gate lines from outer layer of the TFT. Non-uniformity in the gate insulation layer may cause mura effects, especially when displaying low grey scale images.